The invention relates to a method of fabricating a semiconductor substrate, and more particularly to manufacturing a transistor having elevated source and drain regions.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths typically greater than 2 microns) to short-channel devices (i.e., channel lengths typically less than 2 microns).
As field effect transistor channel lengths (i.e., gate widths) became smaller than about 3 microns, so-called short channel effects began to become increasingly significant. As a result, device design and consequently process technology have to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example, as device dimensions are reduced and the supply voltage remains constant, the lateral electric field generated within the substrate increases. If the field becomes strong enough, it can give rise to so-called hot-carrier effects. Hot-carrier effects cause unacceptable performance degradation in n-type transistor devices built with conventional drain structures if their channel lengths are less than 2 microns.
A preferred method of overcoming this problem is to provide lightly doped drain xe2x80x9c(LDD)xe2x80x9d regions within the substrate relative to the channel region in advance of the source and drain regions. The LDD regions are provided to be doped lighter than the source and drain regions. This facilitates sharing of the voltage drop by the drain in the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD n-type transistors. The LDD regions absorb some of the voltage drop potential into the drain, thus reducing hot carrier effects. As a result, the stability of the device is increased.
However, further shrinking of the gate width (i.e., shorter channel length) makes the LDD region of a conventional transistor less effective. For example, shorter channel lengths require the LDD length to be reduced to ensure sufficient semiconductive material between the diffusion regions to prevent conductance when the gate voltage is off. One way of attending to such problems is to displace the predominant portion of the source and drain regions outwardly away from the substrate by elevating them. For example, a thin (e.g., 200 nm) epitaxial layer of monocrystalline silicon can be selectively grown from exposed monocrystalline source and drain substrate areas within an epi reactor, and provided with sufficiently high conductivity doping to effectively provide source and drain regions. The lighter doped LDD regions can be provided within the substrate immediately below the elevated source and drain. Thus, a channel of sufficient length is effectively provided despite the smaller width gate. The resulting transistor has significantly reduced short channel effects.
FIGS. 1A to ID are cross-sectional views for explaining a conventional method of manufacturing transistors having elevated drain and source regions. Referring to FIG. 1A, a field oxide isolation structure 11 is formed on a silicon substrate 10 to define active and inactive regions. A gate structure having a gate oxide film 12, a gate electrode 13 and a mask insulating film 14 are formed on a portion of the silicon substrate 10 within the active region. Lightly doped regions 15 are formed within the silicon substrate 10 by an ion implantation step. A double gate spacer 16 having an oxide film 16a and a nitride oxide film 16b formed (FIG. 1B). An epitaxial silicon layer 17 is selectively grown on the exposed portion of the silicon substrate 10 using a chemical vapor depositon process without doping (FIG. 1C). The epitaxial silicon layer 17 grows at slower rate at a location adjacent to the double gate spacer 16 than elsewhere. As a result, a large facet 18 is formed at a junction where of the epitaxial silicon layer 17 meets the double gate spacer 16. While the facet 18 is being formed, a self-aligned epitaxial silicon sliver (SESS) 19 is formed below the double gate spacer 16. An ion implantation step is performed to heavily dope the silicon layer 17 (FIG. 1D). Thereafter, an annealing process is performed to activate the ion injected into the silicon layer 17, thereby completing the formation of the source and drain regions.
Referring to FIG. 2, the conventional transistor thus fabricated may have a portion of the lightly doped region 15, below the gate spacer 16 and adjacent to the channel, extend deeper into the substrate than the desired depth. This results since when the ion implantation step is performed to dope the epitaxial silicon layer 17, the ions being injected into the silicon layer 17 via the facet 18 are generally driven further into the silicon layer 17 than the ions in other region. Therefore, the large facet 18 may contribute to deterioration of the short channel characteristic and the hot carrier suppression capability of the transistors. In addition, during the annealing process, a significant number of the impurity ions may diffuse into the self-aligned epitaxial silicon sliver 19, which would result in lose of some of the benefits of having the lightly doped region 15 interface between the heavily doped silicon layer 17 and the channel.
One method used to solve the above problem bas been to planarize the silicon layer 17 to remove the facet 18 and also to restructure junction structure to decrease hot carrier effects. However, such a solution becomes difficult to apply as the device shrinks to 0.13 micron and smaller.
In one embodiment, a method of manufacturing a transistor having an elevated drain in a substrate includes forming a gate structure on the substrate. A first doped region adjacent to one end of the gate structure is provided, the first doped region having a first dopant concentration level. A second doped region overlying the first doped region is formed, the second doped region having a second dopant concentration level. A third doped region overlying the second doped region is formed, the third doped region having a third dopant concentration level different from the second dopant concentration level.